Typically, MOS transmission gates utilize two transistors coupled in parallel to form input and output nodes and are controlled by a control signal. Such transmission gates are a source of error voltages created by parasitic capacitance associated therewith. A compensating transistor which is matched with the two parallel coupled transistors is typically connected to one of the input or output nodes of the two coupled transistors. The compensating transistor is controlled by a complement control signal. Due to a limitation of the amount of voltage which may by applied to current electrodes of the two transistors, a P-channel and an N-channel transistor are frequently used for each of the two transistors. Such a configuration is commonly referred to as a CMOS switch or transmission gate. Parasitic capacitance associated with the gate-source and gate-drain interface couples charge from the control signals to both an input and an output terminal of the transmission gate. Frequently, one of the input/output terminals is directly coupled to either a ground reference or to a voltage source in which case the parsitic charge coupling to a terminal connected in this manner does not produce an error. However, when an input/output terminal of a transmission gate is coupled to a high impedance, parasitic charge coupling to the high impedance node creates an error voltage. This error voltage is typically referred to as control signal feedthrough. Therefore, a compensating transmission gate which is substantially matched with the two transmission gates is connected to the compensated node of the two transmission gates and also controlled by the complementary control signals. The compensating device utilizes offsetting charge to limit an error voltage resulting from transients occurring during the switching action of the transmission gate. However, unless clock skew, the time of delay between the complementary control signals, is zero, total charge cancellation is not achieved resulting in an error voltage.